The JK Flip Flop
From the previous tutorial we now know that the basic gated SR NAND flip flop suffers from two basic problems: number one, the S = 0 and R = 0 condition (S = R = 0) must always be avoided, and number two, if S or R
change state while the enable input is high the correct latching action
may not occur. Then to overcome these two fundamental design problems
with the SR flip-flop design, the JK flip Flop was developed.
This simple
JK flip Flop is the most widely used of
all the flip-flop designs and is considered to be a universal flip-flop
circuit. The sequential operation of the JK flip flop is exactly the
same as for the previous SR flip-flop with the same “Set” and “Reset”
inputs. The difference this time is that the “JK flip flop” has no
invalid or forbidden input states of the SR Latch even when
S and
R are both at logic “1”.
The
JK flip flop is basically a gated
SR Flip-flop
with the addition of a clock input circuitry that prevents the illegal
or invalid output condition that can occur when both inputs
S and
R
are equal to logic level “1”. Due to this additional clocked input, a
JK flip-flop has four possible input combinations, “logic 1″, “logic 0″,
“no change” and “toggle”. The symbol for a JK flip flop is similar to
that of an
SR Bistable Latch as seen in the previous tutorial except for the addition of a clock input.
The Basic JK Flip-flop
Both the
S and the
R inputs of the previous SR bistable have now been replaced by two inputs called the
J and
K inputs, respectively after its inventor Jack Kilby. Then this equates to:
J = S and
K = R.
The two 2-input
AND gates of the gated SR bistable have now been replaced by two 3-input
NAND gates with the third input of each gate connected to the outputs at
Q and
Q. This cross coupling of the SR flip-flop allows the previously invalid condition of
S = “1” and
R = “1” state to be used to produce a “toggle action” as the two inputs are now interlocked.
If the circuit is now “SET” the
J input is inhibited by the “0” status of
Q through the lower
NAND gate. If the circuit is “RESET” the
K input is inhibited by the “0” status of
Q through the upper
NAND gate. As
Q and
Q are always different we can use them to control the input. When both inputs
J and
K are equal to logic “1”, the JK flip flop toggles as shown in the following truth table.
The Truth Table for the JK Function
same as
for the
SR Latch |
Input |
Output |
Description |
| J |
K |
Q |
Q |
| 0 |
0 |
0 |
0 |
Memory
no change |
| 0 |
0 |
0 |
1 |
| 0 |
1 |
1 |
0 |
Reset Q » 0 |
| 0 |
1 |
0 |
1 |
| 1 |
0 |
0 |
1 |
Set Q » 1 |
| 1 |
0 |
1 |
0 |
toggle
action |
1 |
1 |
0 |
1 |
Toggle |
| 1 |
1 |
1 |
0 |
Then the JK flip-flop is basically an SR flip flop with feedback
which enables only one of its two input terminals, either SET or RESET
to be active at any one time thereby eliminating the invalid condition
seen previously in the SR flip flop circuit. Also when both the
J and the
K
inputs are at logic level “1” at the same time, and the clock input is
pulsed either “HIGH”, the circuit will “toggle” from its SET state to a
RESET state, or visa-versa. This results in the JK flip flop acting more
like a T-type toggle flip-flop when both terminals are “HIGH”.
Although this circuit is an improvement on the clocked SR flip-flop
it still suffers from timing problems called “race” if the output
Q changes state before the timing pulse of the clock input has time to go “OFF”. To avoid this the timing pulse period (
T ) must be kept as short as possible (high frequency). As this is sometimes not possible with modern TTL IC’s the much improved
Master-Slave JK Flip-flop was developed.
The master-slave flip-flop eliminates all the timing problems by
using two SR flip-flops connected together in a series configuration.
One flip-flop acts as the “Master” circuit, which triggers on the
leading edge of the clock pulse while the other acts as the “Slave”
circuit, which triggers on the falling edge of the clock pulse. This
results in the two sections, the master section and the slave section
being enabled during opposite half-cycles of the clock signal.
The
TTL 74LS73
is a Dual JK flip-flop IC, which contains two individual JK type
bistable’s within a single chip enabling single or master-slave toggle
flip-flops to be made. Other JK flip flop IC’s include the 74LS107 Dual
JK flip-flop with clear, the 74LS109 Dual positive-edge triggered JK
flip flop and the 74LS112 Dual negative-edge triggered flip-flop with
both preset and clear inputs.
Dual JK Flip-flop 74LS73
Other Popular JK Flip-flop ICs
| Device Number |
Subfamily |
Device Description |
| 74LS73 |
LS TTL |
Dual JK-type Flip Flops with Clear |
| 74LS76 |
LS TTL |
Dual JK-type Flip Flops with Preset and Clear |
| 74LS107 |
LS TTL |
Dual JK-type Flip Flops with Clear |
| 4027B |
Standard CMOS |
Dual JK-type Flip Flop |
The Master-Slave JK Flip-flop
The
Master-Slave Flip-Flop is basically two gated SR
flip-flops connected together in a series configuration with the slave
having an inverted clock pulse. The outputs from
Q and
Q
from the “Slave” flip-flop are fed back to the inputs of the “Master”
with the outputs of the “Master” flip flop being connected to the two
inputs of the “Slave” flip flop. This feedback configuration from the
slave’s output to the master’s input gives the characteristic toggle of
the JK flip flop as shown below.
The Master-Slave JK Flip Flop
The input signals
J and
K are connected to the gated “master” SR flip flop which “locks” the input condition while the clock (
Clk)
input is “HIGH” at logic level “1”. As the clock input of the “slave”
flip flop is the inverse (complement) of the “master” clock input, the
“slave” SR flip flop does not toggle. The outputs from the “master” flip
flop are only “seen” by the gated “slave” flip flop when the clock
input goes “LOW” to logic level “0”.
When the clock is “LOW”, the outputs from the “master” flip flop are
latched and any additional changes to its inputs are ignored. The gated
“slave” flip flop now responds to the state of its inputs passed over by
the “master” section.
Then on the “Low-to-High” transition of the clock pulse the inputs of
the “master” flip flop are fed through to the gated inputs of the
“slave” flip flop and on the “High-to-Low” transition the same inputs
are reflected on the output of the “slave” making this type of flip flop
edge or pulse-triggered.
Then, the circuit accepts input data when the clock signal is “HIGH”,
and passes the data to the output on the falling-edge of the clock
signal. In other words, the
Master-Slave JK Flip flop is a “Synchronous” device as it only passes data with the timing of the clock signal.
In the next tutorial about
Sequential Logic Circuits, we will look at
Multivibrators that are used as waveform generators to produce the clock signals to switch sequential circuits.
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